I. Field of the Disclosure
The technology of the disclosure relates generally to data transfer between hardware devices and cache memory constructs, and more particularly to control of cacheable memory interface frequencies.
II. Background
Electronic devices, such as mobile phones, personal digital assistants (PDAs), and the like, are commonly manufactured using application specific integrated circuit (ASIC) designs. Developments in achieving high levels of silicon integration have allowed creation of complicated ASICs and field programmable gate array (FPGA) designs. These ASICs and FPGAs may be provided in a single chip to provide a system-on-a-chip (SOC). An SOC provides multiple functioning subsystems on a single semiconductor chip, such as for example, processors, multipliers, caches, and other electronic components. SOCs are particularly useful in portable electronic devices because of their integration of multiple subsystems that can provide multiple features and applications in a single chip. Further, SOCs may allow smaller portable electronic devices by use of a single chip that may otherwise have been provided using multiple chips.
In applications where reduced power consumption is desirable, a frequency of a cacheable memory interface (CMI), such as cache memory and cache coherency interconnects, may be lowered, but lowering the frequency lowers performance of the CMI. If lowering the CMI frequency increases latencies beyond latency requirements or conditions for the subsystems coupled to the CMI, the performance of the subsystem may degrade or fail entirely. Rather than risk degradation or failure, the CMI clock may be set to higher frequencies to reduce latency and provide performance margin, but providing higher frequencies consumes more power.